Author(s): Guo, YM (Guo, Yimeng); Li, JX (Li, Jiangxu); Zhan, XP (Zhan, Xuepeng); Wang, CW (Wang, Chunwen); Li, M (Li, Min); Zhang, B (Zhang, Biao); Wang, ZR (Wang, Zirui); Liu, YY (Liu, Yueyang); Yang, KN (Yang, Kaining); Wang, H (Wang, Hai); Li, WY (Li, Wanying); Gu, PF (Gu, Pingfan); Luo, ZP (Luo, Zhaoping); Liu, YJ (Liu, Yingjia); Liu, PT (Liu, Peitao); Chen, B (Chen, Bo); Watanabe, K (Watanabe, Kenji); Taniguchi, T (Taniguchi, Takashi); Chen, XQ (Chen, Xing-Qiu); Qin, CB (Qin, Chengbing); Chen, JZ (Chen, Jiezhi); Sun, DM (Sun, Dongming); Zhang, J (Zhang, Jing); Wang, RS (Wang, Runsheng); Liu, JP (Liu, Jianpeng); Ye, Y (Ye, Yu); Li, XY (Li, Xiuyan); Hou, YL (Hou, Yanglong); Zhou, W (Zhou, Wu); Wang, HW (Wang, Hanwen); Han, Z (Han, Zheng)

Source: NATURE DOI: 10.1038/s41586-024-07438-5  Early Access Date: MAY 2024  Published Date: 2024 MAY 29  

Abstract: Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis 1-3 . Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures 4,5 , as well as hetero-2D layers with different carrier types 6-8 , have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe2 (refs. 9-17 ) and MoS2 (refs. 11,18-28 )) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS2, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS2 can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm2 V-1 s-1, on/off ratios reaching 106 and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.

We develop a method for high-density vertical stacking of active-device multi-layers, implementing memory and logic functions, using unique VIP-FETs where a van der Waals intercalation layer modulates the p- or n-type nature of the FETs.