Title: Fundamentals, modeling and design of small slope, beyond CMOS transistors for energy efficient integrated circuits 

Speaker: Prof. David Esseni（University of Udine, Italy）  

Time: June 6, 2016 14:00PM 

Venue: No.101 meeting room of the library, IOS, CAS 

Abstract: The performance of most integrated circuits is today energy limited, in the sense that circuits simply do not have the energy budget sufficient for the full exploitation of their potential performance. Such a utilization wall led to the so called dark silicon age, where significant fractions of the transistors and gates available on a chip are idle or significantly underclocked to meet power constraints [1]. The main origin of such utilization wall is that, after about the beginning of years 2000, in new CMOS technology generation it has been impossible to scale the power supply voltage, VDD, whose value has reached a plateau at about 1V. The impossibility to scale VDD, in turn, was due to the fact that the corresponding degradation of the dynamic performance could no longer be mitigated with a reduction of the threshold voltage VT, because this would imply an exponential increase of the standby energy, which has become a significant fraction of the overall energy dissipation in integrated circuits. In CMOS technologies new channel materials (e.g. III-V semiconductors) are being explored in order to reduce the power supply and preserve a good performance, however the fundamental limit of a sub-threshold swing larger than 60mV/dec is a serious impediment to a drastic reduction of VT and VDD in MOSFET based technologies. Consequently, more innovative device concepts have been recently explored, such as Tunnel FETs, Negative Capacitance FETs and Piezoelectric FETs, and are sometimes referred to as small slope transistors. Several implementations of TFETs have been reported in experiments [2], and many more possible embodiments have been explored by means of simulations. Nevertheless the progress of TFETs is admittedly lagging behind expectations and a number of issues have been recognized to plague their successful development. In this presentation I will discuss some important challenges and opportunities related to Tunnel FETs featuring different material and architecture options. I will show that it is arguably difficult for Tunnel FETs to compete with conventional CMOS FETs when the channel length approaches LG~10nm. Finally I will comment on the working principle and the perspectives of some small slope transistor concepts other than Tunnel FETs.

References:

[1] M. B. Taylor, “Is Dark Silicon Useful?—Harnessing the four horsemen of the coming dark silicon apocalypse”, Design Automation Conference (DAC), 2012.

[2] A. C. Seabaugh and Q. Zhang, “Low-voltage tunnel transistors for beyond CMOS logic”, Proc. IEEE, vol.98, 2095-2110, 2010.

Biography：David Esseni received the Ph.D. in Electronic Engineering from the University of Bologna and he is now professor of electrincs at the University of Udine, Italy. During year 2000 he was a visiting scientist at Bell Labs – Lucent Technologies, Murray Hill (NJ-USA), while in year 2013 he was a visiting professor at University of Notre Dame (IN-USA) supported by a Fulbright Fellowship.

D. Esseni is the author of numerous papers and of several book chapters in his fields of expertise, futhermore he is co-author of the book “Nanoscale MOS transistors: Semi-classical transport and applications”, Cambridge University Press, 2011. D. Esseni is a Fellow of the IEEE Electron Devices Society and he is Associate Editor of IEEE Transactions on Electron Devices since 2008. D. Esseni has served or is serving as a member of the technical commitees in several conferences including the IEDM, IRPS, SISPAD and ESSDERC.