Title:CMOS-Memristor Hybrid Circuits: Devices, Integration, Architecture, and Applications 

Speaker: Prof. K.-T. Tim Cheng (University of California, Santa Barbara) 

Time: 15:30 PM, June 24, 2013         

Venue: LED Meeting Room, No.5 Research Building, IOS, CAS    

　　Abstract: In this talk, we give an overview of our recent research efforts on monolithic 3D integration of CMOS and memristive nanodevices. The project is under Center of 3D Hybrid CMOS-Nano Circuits funded by the AFOSR and consists of 9 faculty groups of four universities from multiple disciplines, including computer engineering, electrical engineering, materials science, and physics. These proposed hybrid circuits combine a CMOS subsystem with several layers of nanowire crossbars, consisting of arrays of two-terminal memristors, all connected by an area-distributed interface between the CMOS subsystem and the crossbars. This approach combines the advantages of CMOS technology, including its high flexibility, functionality and yield, with the extremely high density of nanowires, nanodevices and interface vias. As a result, the 3D hybrids can overcome limitations pertinent to other 3D integration techniques (such as through-silicon vias) and enable 3D circuits with unprecedented memory density (up to 10^14 bits on a single 1-cm^2 chip) and aggregate interlayer communication bandwidth (up to 10^18 bits per second per cm^2) at manageable power dissipation. 

　　Biography: Cheng received his Ph.D. in EECS from the Univ. of California, Berkeley in 1988. He worked at Bell Laboratories from 1988 to 1993 and joined the faculty at the University of California, Santa Barbara in 1993 where he is now Associate Vice Chancellor for Research and Professor of ECE. He was the founding director of UCSB’s Computer Engineering Program (1999-2002) and Chair of the ECE Department (2005-2008). He held a Visiting Professor position at Taiwan TsingHua Univ. (1999), Univ. of Tokyo, Japan (2008), and Hong Kong Univ. of Science and Technology (2012) and is holding Chair Professorship at Zhejiang Univ. China. His current research interests include mobile embedded systems, SoC and flexible electronics design, validation and test, and multimedia computing. He has published more than 350 technical papers, co-authored five books, supervised 30 PhD dissertations, and holds 12 U.S. Patents in these areas. Cheng currently serves as Director for DoD/MURI Center for 3D hybrid circuits which aim at integrating CMOS with high-density memristors. He also served on the executive committee, as a research thrust leader, of the SRC/FCRP Gigascale System Research Center.Cheng, an IEEE fellow, received 10 Best Paper Awards from various IEEE conferences and journals. He has also received the 2004-2005 UCSB College of Engineering Outstanding Teaching Faculty Award. He served as Editor-in-Chief of IEEE Design and Test of Computers (2006-2009) and was a board member of IEEE Council of Electronic Design Automation’s Board of Governors, IEEE Computer Society’s Publication Board, and working groups of International Technology Roadmap for Semiconductors (ITRS). He has also served as General and Program Chair for several international conferences including 2012 IEEE International Test Conference.